As memory density and speed continue to increase in memory devices and as the demand for ever larger memory arrays continues, the die real estate occupied by both the memory circuits and associated peripheral logic circuits is of critical importance. Particularly peripheral logic circuits are becoming very large and increasingly difficult to fit in a defined memory device area. In addition, when delay stages are required in the peripheral logic circuit, this further adds to the problem as delay stages are known for their large size due to the requirement for resistors, capacitors and metal options to produce different timing delays.
Delay elements are typically employed in high speed double data rate memory devices which require data shifters for shifting data in a write cycle. For example, in some double data rate memory devices it is known that a two clock cycle latency period is required before data, for example, address data, can be delivered to a memory core for a write operation from the time that the data is latched at an input buffer into the memory device.
The data shifters shift the latched data with the clock signal used to latch the data to allow the data to be delivered at the time necessary for a properly timed memory operation.
However, at all times, data leaving the shifters still arrives faster than desired, and delay stages are typically used to make sure that the data from the shifter outputs are delayed in synchronism with the clock loading new data into the input buffer, to thereby prevent incorrect memory access operations.
FIG. 1 illustrates, as an example, one prior art circuit which employs address data shifters and associated delay elements. The FIG. 1 circuit is utilized to produce bank addresses for a memory device on lines BA_W&lt;.phi.&gt;, BA_W&lt;1&gt;, BA_W&lt;2&gt;, and BA_W&lt;3&gt;. These bank address lines are also designated by respective data output lines 29a . . . 29d. The bank addresses are derived from address data received on input lines 17a . . . 17d of input buffer 11. It should be noted that for purposes of simplification of explanation, only four data input lines 17a . . . 17d and four data output lines 29a . . . 29d are illustrated in FIG. 1. However, any number of input lines 17 and output lines 29 can be provided as needed for a particular memory device and the number of input lines 17 need not equal the number of output lines 29.
The noted bank address selection signals on lines 29a . . . 29d are generated from input data addresses which are applied as data in on input lines 17a . . . 17d of a memory device. The multi-bit address data is latched in by a clock signal on line 15 at each of the respective one-bit latches 13a . . . 13d which are provided in an input buffer circuit 11. The address data latched at the input buffer circuit 11 is in turn decoded by a decoder 13 to produce the bank address selection signals BA_W&lt;0:3&gt;. A shift register circuit 19 is provided, having individual shift register elements 29a . . . 29d which delay the decoded bank select signals by, for example, two cycles of the clock signal appearing on line 15. In addition, the shift register circuit 19 also has associated with each shift element 21a . . . 21d, a respective delay element 23a . . . 23d. The delay elements ensure that the bank select signals appearing on lines 29a . . . 29d are property synchronized with the clock signal 15 which is loading new address data into the latches 13a . . . 13d of input buffer 11.
As shown in FIG. 1, the output bank select data BA_W&lt;0:3&gt; at each of the delay circuits 23a . . . 23d are respectively provided to multiplexers 27a . . . 27d on a first path. The multiplexers also receive from decoder 13 the same bank select information on a second path, which does not pass through the shift register elements 21a . . . 21d or associated delay elements 23a . . . 23d. Mutltiplexers 27a . . . 27d are thus each provided with a shifted and delayed address signal on one input, and an unshifted, undelayed address signal on another input. The multiplexers 27a . . . 27d each select one of the applied inputs and provides it as an output in response to a selection signal denoted LWENA/LWENAi. The selection signal LWENA/LWENAi is thus used to select which of the outputs of the delay stage 23a or the unshifted undelayed output from decoder 13 is applied to the respective bank address signal lines 29a . . . 29d. When the selection signal LWENA/LWENAi goes high the shifted/delayed input of a multiplexer is selected, and when it goes low the unshifted/undelayed input is selected. Since the address information only needs to be shifted during a write operation, the selection signal goes high for a memory write operation and low for a memory read operation.
As illustrated by FIG. 6, to properly time the shifted data a delay 23a . . . 23d is associated with each of the shift register elements 21a . . . 21d. This requires a considerable amount of real estate on a die to implement the delay elements 23a . . . 23d for the reasons noted.
A simplified peripheral logic input data shift circuit which requires less delay elements would be desirable.